hardware

Processor interrupt handling is one of the must-have knowledge in computer architecture. Under Intel’s x86 processor, interrupts can be categorized as external interrupts, exceptions, and traps. External interrupts come from the hardware and occur randomly, while exceptions are the result of error conditions detected during the execution of instructions within the processor. Traps, on the other hand, are generated by the program and are usually triggered by instructions such as INT n, INTO, and so on. In x86 processors, interrupt handlers handle interrupts, exception handlers handle exceptions, and system call service programs handle traps. These handlers can be located anywhere in the memory space and can have different privilege levels.Intel processors use interrupt gates, trap gates, and task gates to define the entry addresses of handlers. Of these, … Read more

Memory management is a very important part of the operating system. With the continuous development of computer technology, the way of memory management is also evolving. In this article, we will introduce several common memory management methods for the Intel 64 system. Flat-page memory management is a relatively simple way of memory management. It uses page-based management to mask out segment-based management. Specifically, it maps logical addresses directly to linear addresses, defines a code segment and a data segment, and the size of both segments is 4 GB.The advantage of this approach is that it is simple and easy to understand, but its disadvantage is that it does not allow for multi-process memory isolation. In order to solve the problem of multi-process memory isolation, a protected flat memory … Read more

In segment-page memory management, the linear address of a segment is divided into linear pages of equal size (4KB, 4MB or 2MB, etc.). Physical memory space is also divided into physical pages of equal size. The operating system maintains a page table to manage the mapping of linear pages to physical pages. The page table is divided into two levels in the IA-32 architecture, the page catalog and the page table. The page catalog is an array whose elements are called page directory entries (PDEs), and each page directory entry describes a page table. The size of the page directory is one page (4KB) and there are 1024 page directory entries in a page directory. The size of a page directory entry is 4 bytes. The size of … Read more

The IA-32 system provides a segmented page-based memory management mechanism, with segmentation followed by paging. Page-based is provided to support virtual memory. Segment: The processor’s addressable linear memory space is divided into segments of varying sizes. A segment is a contiguous interval in the linear address space. Segments can hold code, data, stacks, or other data structures. The attribute information of a segment is described by its corresponding segment descriptor. A segment descriptor is a data structure that Intel manages using a segment descriptor table. The segment descriptor table can be up to 64KB. When G is 0, segments are measured in bytes, and the maximum segment length is 1MB. when G is 1, segments are measured in pages (4kb). The maximum segment length is 4GB. DPL is … Read more

Memory is the storage space that can be directly accessed by the processor. To speed up memory access, computer systems usually provide some cache, which is usually managed by hardware. I/O devices consist of I/O controllers and physical devices, and the processor manages the physical devices through the I/O controllers.The I/O controllers are mainly composed of control and status registers (CSRs) and data registers. The processor reads CSRs to obtain device status, writes CSRs to control device actions, and reads and writes data registers to exchange data. The kernel usually abstracts I/O devices into a set of registers and gives an I/O address to a register. The processor accesses the I/O registers through the I/O address. Many device registers in modern computer systems can be mapped into the … Read more