Common memory management for intel 64 systems

Memory management is a very important part of the operating system. With the continuous development of computer technology, the way of memory management is also evolving. In this article, we will introduce several common memory management methods for the Intel 64 system.

Flat-page memory management is a relatively simple way of memory management. It uses page-based management to mask out segment-based management. Specifically, it maps logical addresses directly to linear addresses, defines a code segment and a data segment, and the size of both segments is 4 GB.The advantage of this approach is that it is simple and easy to understand, but its disadvantage is that it does not allow for multi-process memory isolation.

In order to solve the problem of multi-process memory isolation, a protected flat memory management approach can be used. Specifically, it defines a kernel code segment, a kernel data segment, a user code segment, and a user data segment, each with a base address of 0 and a size of 4 GB. processes use the kernel segment when executing kernel code and the user segment when executing user code. The advantage of this approach is that it allows for multi-process memory isolation, but its disadvantage is that it requires address translation, which affects efficiency.

Multi-segmented memory management is an approach that uses segmented management completely, blocking out page management. It allows for multi-process memory isolation, but it requires address translation, which also affects efficiency.

Page-based memory management based on physical address expansion is an approach that supports a larger physical address space. It introduces Physical Address Expansion (PAE) mechanism to support 36-bit physical addresses. In this management mode, the physical address space is expanded to 64GB, but the linear address space remains 4GB. page directories and page table entries are expanded to 64 bits, and thus the number of entries in a page directory or page table becomes 512, and a page directory describes only 1GB of linear address space. So a page directory pointer table (PDP) with only four table entries was introduced. the CR3 points to the PDP. the address translation mechanism was modified. When the PS bit in a page directory entry is set to 1. the page it describes becomes a 2MB page.

In 64-bit mode, segments are normally turned off, and segment boundary checking is no longer done. the base address processors of CS, DS, ES, and SS are collectively treated as 0. However, FS and GS can be anything other than 0, and the base address of FS or GS is added to the logical address when converting it to a prior address. the base address of FS and GS is a 64-bit address, and in compatibility mode, only the lower 32 bits are used, which are recorded in the MSR. In 64-bit mode, the management of memory relies entirely on the paging mechanism.The Intel64 architecture extends the PAE mechanism to support 64-bit linear addresses and 52-bit physical addresses. The extensions include:

  1. The page directory pointer table was expanded to 512 entries.
  2. A fourth-level page mapping table, PML4, was introduced, each of whose entries can point to a PDP.
  3. All Level 4 page map table entries were expanded to 64 bits.
  4. The PS flag in the page catalog entries is used to control 4KB and 2MB pages.
  5. All page table entries have a new Execute Prohibit flag EXB in bit 63.