Processor interrupt handling is one of the must-have knowledge in computer architecture. Under Intel’s x86 processor, interrupts can be categorized as external interrupts, exceptions, and traps. External interrupts come from the hardware and occur randomly, while exceptions are the result of error conditions detected during the execution of instructions within the processor. Traps, on the other hand, are generated by the program and are usually triggered by instructions such as INT n, INTO, and so on.
In x86 processors, interrupt handlers handle interrupts, exception handlers handle exceptions, and system call service programs handle traps. These handlers can be located anywhere in the memory space and can have different privilege levels.Intel processors use interrupt gates, trap gates, and task gates to define the entry addresses of handlers. Of these, interrupt gates and trap gates are portals into exception handlers. Selectors and offsets together define the entry address of a handler. The IF flag is cleared when an interrupt gate enters a handler, while the IF flag remains unchanged when a trap gate enters a handler.
The Intel processor defines an interrupt vector number for each interrupt and exception and establishes a correspondence between the interrupt vector number and the gate through the interrupt descriptor table (IDT).The IDT can reside anywhere in the linear address space.The Intel processor provides a dedicated IDTR register to record the base address and boundary information for the IDT.The Intel processor defines 256 interrupt vector numbers, of which 0 to 31 are reserved by the processor.
Exceptions in the processor can be categorized into fault class exceptions and termination class exceptions. Faulty exceptions can be corrected, while terminated exceptions are serious errors that cannot be resolved by the processor itself. For safety, control can be transferred through interrupt gates or trap gates only to code segments of the same or higher privilege level. Typically, handlers are defined in kernel code segments (privilege level 0 code segments).
When an interrupt occurs, the processor automatically presses a number of parameters onto the top of the stack, where EFLAGS is the system state before the interrupt or exception occurred, SS:ESP is the top of the user stack before the interrupt or exception occurred, and CS:EIP is the return address of the interrupt or exception. 64-bit mode requires that the handler must be in a 64-bit code segment, and thus the interrupt and trapdoor descriptors are expanded to 16 bytes, where offsets are expanded to 64 bits; the IDT finds that only gate descriptors with the new format; the stack width becomes 64 bits, and when an interrupt occurs, it unconditionally presses in the stack pointer (SS:RSP) SS is forced to be set to NULL when it is necessary to toggle the stack; an Interrupt Stack Table (IST) mechanism is added to allow specific interrupts or exceptions to specify a specialized stack.