Segmented Memory Management Overview

In segment-page memory management, the linear address of a segment is divided into linear pages of equal size (4KB, 4MB or 2MB, etc.). Physical memory space is also divided into physical pages of equal size. The operating system maintains a page table to manage the mapping of linear pages to physical pages. The page table is divided into two levels in the IA-32 architecture, the page catalog and the page table.
The page catalog is an array whose elements are called page directory entries (PDEs), and each page directory entry describes a page table. The size of the page directory is one page (4KB) and there are 1024 page directory entries in a page directory. The size of a page directory entry is 4 bytes. The size of a page table is one page (4KB). The size of a page table entry is 4 bytes, so a page table can describe up to 1024 linear pages.
Physical pages are pre-divided and their start position must be on a 4KB (2^12) boundary. So the lower 12 bits are all zeros. Then the lower 12 bits can store while outside information.
P is the presence bit. r/w is the read/write flag bit. u/s is the user flag bit, with a 0 indicating a super user. a is the access flag bit. d is the dirty flag bit.
The PAT flag is replaced with the PS flag in the page catalog entry to indicate the physical page size.
The CR3 register is dedicated to the physical address of the page directory currently in use, so CR3 is also called the page directory base address register. As long as the process is active, its page directory should always reside in memory.
The page directory entry can also point directly to a physical page to speed up address translation, which is usually set to 4MB pages occupied by the operating system kernel. The page catalog entry has a PS address of 1 thing, which describes a 4MB page and no longer a page table.
The paging mechanism is initiated by the operating system kernel and is initiated by setting the PG flag in CR0 to 1.
After the paging mechanism is initiated, each linear address needs to go through a page directory and page table translation.The IA-32 architecture incorporates a cache TIB that stores the most recently used page directory and page table entries.Frequent flushes of the TIB are handled by the operating system kernel. When page directory and table entries are changed, the kernel must invalidate the corresponding entries in the TIB. All contents of the TIB (except the Global page) are automatically invalidated when CR3 is changed.The INVLPG instruction sets the specified entry in the TLB to invalid.