Segment Memory Management Overview

The IA-32 system provides a segmented page-based memory management mechanism, with segmentation followed by paging. Page-based is provided to support virtual memory.
  • Segment: The processor’s addressable linear memory space is divided into segments of varying sizes. A segment is a contiguous interval in the linear address space. Segments can hold code, data, stacks, or other data structures. The attribute information of a segment is described by its corresponding segment descriptor. A segment descriptor is a data structure that Intel manages using a segment descriptor table. The segment descriptor table can be up to 64KB.
    • When G is 0, segments are measured in bytes, and the maximum segment length is 1MB. when G is 1, segments are measured in pages (4kb). The maximum segment length is 4GB.
    • DPL is the privilege level of the segment, and its value is between 0 and 3.
    • S is the system flag used to distinguish the class of the segment. 0 indicates a system segment and 1 indicates a user segment.
    • Type is the type of the segment:
      • For system segments. The Type field consists of 4 bits and can represent one of the 16 system segment types.
      • For user segments.
        • A third bit of 0 indicates a data segment. at which point the second bit indicates the direction of address expansion (0 indicates the direction of major expansion) and the first bit indicates whether the segment is writable.
        • A third bit of 1 indicates a code segment. at which point the second bit is a compatibility flag (0 indicates non-compatibility). The first bit is a readable bit.
        • Bit 0 is an access bit. a 0 indicates that the segment has not been accessed.
    • The D/B flag indicates the effective address and operand length.
    • The L flag appears only in IA-32e mode segments. 1 indicates 64-bit mode.
    • Stack segments are usually downward expanding, read-write data segments.
  • Segment Descriptor Table:
    • Global Descriptor Table (GDT). A GDT must be defined for the system before it enters protected mode. the IA-32 architecture specifically defines a GDTR register to hold information about the current GDT.
    • The Local Descriptor Table (LDT) is a system segment in which local descriptors can be stored, such as the process’s own code segments, data segments, etc. The IA-32 architecture specifically provides an LDTR register to hold information about the currently used LDT.
A segment descriptor can be identified by its index in the segment descriptor table; the identification is called a segment selector. The segment selector is a 16-bit identifier. The second bit is an indicator (TI) indicating the descriptor table to which the index is referenced (0 for GDT). Bits 3-15 indicate the index and mark the location. Bits 0 and 1 are the Request Privilege Level RPL. a segment selector plus an offset uniquely identifies a logical address. A logical address is an address used by a program, not a linear address, and not a physical address.
The IA-32 system provides six segment registers, CS, SS, DS, ES, FS, and GS. each segment register can cache one segment descriptor.