Hardware

Processor interrupt handling is one of the must-have knowledge in computer architecture. Under Intel’s x86 processor, interrupts can be categorized as external interrupts, exceptions, and traps. External interrupts come from the hardware and occur randomly, while exceptions are the result of error conditions detected during the execution of instructions within the processor. Traps, on the other hand, are generated by the program and are usually triggered by instructions such as INT n, INTO, and so on. In x86 processors, interrupt handlers handle interrupts, exception handlers handle exceptions, and system call service programs handle traps. These handlers can be located anywhere in the memory space and can have different privilege levels.Intel processors use interrupt gates, trap gates, and task gates to define the entry addresses of handlers. Of these, interrupt gates and trap gates are portals into exception handlers. Selectors and offsets together define the entry address of a handler. The IF flag is cleared when an interrupt gate enters a handler, while the IF flag remains unchanged when a trap gate enters a handler. The Intel processor defines an interrupt vector number for each interrupt and exception and establishes a correspondence between the interrupt vector number and the gate through the interrupt descriptor table (IDT).The IDT can reside anywhere in the linear address space.The Intel processor provides a dedicated IDTR register to record the base address and boundary information for the IDT.The Intel processor defines 256 interrupt vector numbers, of which 0 to 31 are reserved by the processor. Exceptions in the processor can be categorized into fault class exceptions and termination class exceptions. Faulty exceptions can be corrected, while terminated exceptions are serious errors that cannot be resolved by the processor itself. For safety, control can be transferred through interrupt gates or trap gates only to code segments of the same or higher privilege level. Typically, handlers are defined in kernel code segments (privilege level 0 code segments). When an interrupt occurs, the processor automatically presses a number of parameters onto the top of the stack, where EFLAGS is the system state before the interrupt or exception occurred, SS:ESP is the top of the user stack before the interrupt or exception occurred, and CS:EIP is the return address of the interrupt or exception. 64-bit mode requires that the handler must be in a 64-bit code segment, and thus the interrupt and trapdoor descriptors are expanded to 16 bytes, where offsets are expanded to 64 bits; the IDT finds that only gate descriptors with the new format; the stack width becomes 64 bits, and when an interrupt occurs, it unconditionally presses in the stack pointer (SS:RSP) SS is forced to be set to NULL when it is necessary to toggle the stack; an Interrupt Stack Table (IST) mechanism is added to allow specific interrupts or exceptions to specify a specialized stack. ...

Memory management is a very important part of the operating system. With the continuous development of computer technology, the way of memory management is also evolving. In this article, we will introduce several common memory management methods for the Intel 64 system. Flat-page memory management is a relatively simple way of memory management. It uses page-based management to mask out segment-based management. Specifically, it maps logical addresses directly to linear addresses, defines a code segment and a data segment, and the size of both segments is 4 GB.The advantage of this approach is that it is simple and easy to understand, but its disadvantage is that it does not allow for multi-process memory isolation. In order to solve the problem of multi-process memory isolation, a protected flat memory management approach can be used. Specifically, it defines a kernel code segment, a kernel data segment, a user code segment, and a user data segment, each with a base address of 0 and a size of 4 GB. processes use the kernel segment when executing kernel code and the user segment when executing user code. The advantage of this approach is that it allows for multi-process memory isolation, but its disadvantage is that it requires address translation, which affects efficiency. Multi-segmented memory management is an approach that uses segmented management completely, blocking out page management. It allows for multi-process memory isolation, but it requires address translation, which also affects efficiency. Page-based memory management based on physical address expansion is an approach that supports a larger physical address space. It introduces Physical Address Expansion (PAE) mechanism to support 36-bit physical addresses. In this management mode, the physical address space is expanded to 64GB, but the linear address space remains 4GB. page directories and page table entries are expanded to 64 bits, and thus the number of entries in a page directory or page table becomes 512, and a page directory describes only 1GB of linear address space. So a page directory pointer table (PDP) with only four table entries was introduced. the CR3 points to the PDP. the address translation mechanism was modified. When the PS bit in a page directory entry is set to 1. the page it describes becomes a 2MB page. In 64-bit mode, segments are normally turned off, and segment boundary checking is no longer done. the base address processors of CS, DS, ES, and SS are collectively treated as 0. However, FS and GS can be anything other than 0, and the base address of FS or GS is added to the logical address when converting it to a prior address. the base address of FS and GS is a 64-bit address, and in compatibility mode, only the lower 32 bits are used, which are recorded in the MSR. In 64-bit mode, the management of memory relies entirely on the paging mechanism.The Intel64 architecture extends the PAE mechanism to support 64-bit linear addresses and 52-bit physical addresses. The extensions include: ...

In segment-page memory management, the linear address of a segment is divided into linear pages of equal size (4KB, 4MB or 2MB, etc.). Physical memory space is also divided into physical pages of equal size. The operating system maintains a page table to manage the mapping of linear pages to physical pages. The page table is divided into two levels in the IA-32 architecture, the page catalog and the page table. ...

The IA-32 system provides a segmented page-based memory management mechanism, with segmentation followed by paging. Page-based is provided to support virtual memory. Segment: The processor’s addressable linear memory space is divided into segments of varying sizes. A segment is a contiguous interval in the linear address space. Segments can hold code, data, stacks, or other data structures. The attribute information of a segment is described by its corresponding segment descriptor. A segment descriptor is a data structure that Intel manages using a segment descriptor table. The segment descriptor table can be up to 64KB. ...

Memory is the storage space that can be directly accessed by the processor. To speed up memory access, computer systems usually provide some cache, which is usually managed by hardware. I/O devices consist of I/O controllers and physical devices, and the processor manages the physical devices through the I/O controllers.The I/O controllers are mainly composed of control and status registers (CSRs) and data registers. The processor reads CSRs to obtain device status, writes CSRs to control device actions, and reads and writes data registers to exchange data. The kernel usually abstracts I/O devices into a set of registers and gives an I/O address to a register. The processor accesses the I/O registers through the I/O address. ...